1. Field of the Invention
The present invention relates to electronic devices, and in particular, to packages for electronic devices.
2. Description of Related Art
An IC package typically includes a substrate or chip carrier and one or more chips. In ball-grid arrays (BGA), solder balls are used to connect the IC package to a printed circuit board (PCB). The die or chip within the IC package may use wire bonding, flip-chip technology or tape automated bonding (TAB) to connect the chip to the substrate. A land grid array (LGA) package is essentially the same as a BGA package, except the solder balls are removed. In a chip scale package (CSP), the goal is to achieve a package area no larger than the die itself.
In a folded and stacked BGA (FSBGA) package, multiple chips may be included. The FSBGA package may use two-layer wiring wherein a folded, flexible, polymer substrate has on one surface a first routing layer with metal attachment pads, on the other surface a second routing layer with metal interconnects for interconnecting with the attachment pads, and vias interconnecting the two routing layers. In some designs, the folded flexible tape has a U-shaped configuration which surrounds one or more chips and allows for one or more additional chips to be staked on top of the folded flexible tape to create a multi-chip IC package. This FSBGA package may also be referred to as a folded and stacked CSP (FSCSP) package.
Referring to FIG. 1, a segment 10 of an interconnect routing layer of a FSBGA package is shown. With this FSBGA package, high-speed signals in conductive signal traces 12 need return ground traces 14 that are as close as possible to signal traces 12. As input/output (I/O) speed increases from 66 megahertz (MHz) to 133 MHz, the number of ground traces 14 required may be doubled. Beyond 133 MHz, this number may double again, requiring finer trace lines and vias for the routing. Hence, to deal with increasing I/O speeds in IC packages, the conventional practice is to increase the number of ground traces and reduce the line widths and spacing for the interconnects. In FIG. 1, signal traces 12, ground traces 14, and power traces 16 have a 2:1:1 ratio, requiring 50% of the available routing on the interconnect routing layer to be for power and ground traces 16 and 14.